Member of Scientific Personnel, CERN
June 2023 — Sept. 2023
Implemented an algorithm to overcome data desynchronization between the on-detector front-end ASICs and off-detector FPGA readout systems in the Large Hadron Collider (LHC).
Hi I am Pranav S Murali ,
I’m currently pursing a masters degree at the University of Washington where I’m advised by Prof. Scott Hauck. I have a breath of experience across the hardware side of things on the computing stack from transistor level VLSI Design to application level Embedded Systems Design.
Implemented an algorithm to overcome data desynchronization between the on-detector front-end ASICs and off-detector FPGA readout systems in the Large Hadron Collider (LHC).
Coursework - Computer Architecture I, Computer Architecture II, High-Performance Computer Architecture, Introduction to VLSI, ASIC Design, Capstone Integrated Digital Design Projects, Automatic Layout of ICs and AI for Engineers.
Managed 3 key customers - Tork Motors, Ox Power, and ETO Motors with the design of a suitable Battery Management System (BMS) for Electric Vehicles. Independently drove a project to completion which resulted in the largest Purchase Order received for an off-the-shelf product of ION Energy at that time. Automated a process of BMS Configuration Review by creating a Python tool that reduced customer activation time by 60%.
Designed the electronics for commercial and consumer products Smart Batter, Aerem (now Climec labs), and Seabike for three early-stage startups.
Worked with ROS Toolbox Development Team tom implement the MATLAB function rosgenmsg in C++, fixed existing bugs within the toolbox
Electronics and Communication Engineering