SmartL1-A Trigger Forwarding Algorithm for LHC
SmartL1-A Trigger Forwarding Algorithm for LHC

Implemented an algorithm to overcome data desynchronization between the on-detector front-end ASICs and off-detector FPGA readout systems in the Large Hadron Collider (LHC).

VHDLVersion ControlTestbed
FPGA-accelerated machine learning for Reflection High-Energy Electron Diffraction(RHEED)
FPGA-accelerated machine learning for Reflection High-Energy Electron Diffraction(RHEED)

Deploying a CNN on a FPGA for Reflective High Energy Electron Diffraction(RHEED). The FPGA will be interfaced with a camera to obtain inputs, and perform inference to predict the expected structure of the material.

High Level Synthesis for Machine LearningPythonVivado HLSUltrascale+
Convolution Accelerator for Vision Processing Unit
Convolution Accelerator for Vision Processing Unit

A massively parallel 2D convolution hardware accelerator targeted at Image Processing applications. Performance gain is through parallelism and short I/O datapath. Implemented a tiled array of 6x4 processing elements that computes convolution between a 3x3 pixel array and kernel. Performed floorplanning with FreePDK45 for synthesis and OpenRAM for SRAM macro integration.

SystemVerilogPythonSynopsys Design CompilerIC Compiler
RISC-V Processor on FPGA
RISC-V Processor on FPGA

Designed a 5-stage pipelined RISC-V microprocessor with UART interface using Verilog. Implemented the complete instruction set of RV32I and deployed on an ARTY-A7 100T FPGA running at 100 MHz.

SystemVerilogVerilatorVivadoAssembly
Lightweight Helper Thread for RISC-V Core
Lightweight Helper Thread for RISC-V Core

Designed a lightweight helper thread for the RISC-V Vanilla core used in the HammerBlade manycore. Implemented in a way similar to simultaneous multithreading, with the helper thread having a dedicated ALU while sharing the other resources in the pipeline. Benchmarked the performance of the system with memcpy.

SystemVerilogVerdiCUDA Lite